The present invention relates generally to fabrication of integrated circuit devices having scaled-down dimensions, and more particularly, to fabrication of an ultra-thin active device area on a SOI (semiconductor on insulator) substrate with retention of thicker semiconductor material on the SOI (semiconductor on insulator) substrate.
A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
Referring to FIG. 1, a common component of a monolithic IC is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) 100 which is fabricated with SOI (semiconductor on insulator) technology to avoid having the junction capacitance between the drain and the source of the MOSFET 100 and a semiconductor substrate. In such technology, an insulating box 101 is fabricated on a lower semiconductor substrate 102, and components of the MOSFET 100 are fabricated in a SOI (semiconductor on insulator) substrate 103 disposed above the insulating box 101. The insulating box 101 is comprised of an insulating material such as silicon dioxide when the lower semiconductor substrate 102 is comprised of silicon.
The scaled down MOSFET 100 having submicron or nanometer dimensions includes a drain extension 104 and a source extension 106 formed within the SOI substrate 103. The drain extension 104 and the source extension 106 are shallow junctions to minimize short-channel effects in the MOSFET 100 having submicron or nanometer dimensions, as known to one of ordinary skill in the art of integrated circuit fabrication.
The MOSFET 100 further includes a drain contact region 108 with a drain silicide 110 for providing contact to the drain of the MOSFET 100 and includes a source contact region 112 with a source silicide 114 for providing contact to the source of the MOSFET 100. The drain contact region 108 and the source contact region 112 are fabricated as deeper junctions than the drain extension 104 and the source extension 106 such that a relatively large size of the drain silicide 110 and the source silicide 114 respectively may be fabricated therein to provide low resistance contact to the drain and the source respectively of the MOSFET 100. Thus, referring to FIG. 1, the drain contact region 108 and the source contact region 112 extend down within the SOI substrate 103 to the insulating box 101.
The MOSFET 100 further includes a gate dielectric 116 and a gate structure 118 which may be a polysilicon gate. A gate silicide 120 is formed on the polysilicon gate 118 for providing contact to the polysilicon gate 118. A channel 121 of the MOSFET 100 is formed by the region in the SOI substrate 103 between the drain extension 104 and the source extension 106 under the gate dielectric 116. The MOSFET 100 also includes a spacer 122 disposed on the sidewalls of the polysilicon gate 118 and the gate oxide 116. When the SOI substrate 103 is comprised of silicon, the gate dielectric 116 is typically comprised of silicon dioxide. The spacer 122 may also be comprised of silicon dioxide.
Referring to FIG. 1, as the length dimension of the channel 121 of the MOSFET 100 is scaled down, the depth of the drain extension 104 and the source extension 106 is also scaled down to minimize short-channel effects as known to one of ordinary skill in the art of integrated circuit design, and thus the depth of the SOI substrate 103 is scaled down accordingly. Referring to FIG. 1, the drain contact region 108 and the source contact region 112 extend down within the SOI substrate 103 to the insulating box 101. Thus, as the depth of the SOI substrate 103 is further scaled down, the depth of the drain contact region 108 and the source contact region 112 is also scaled down.
However, a smaller depth of the drain contact region 108 and the source contact region 112 results in a smaller volume of the drain silicide 110 and the source silicide 114 which in turn results in higher series resistance at the drain and the source of the MOSFET 100. Such higher parasitic series resistance degrades the speed performance of the MOSFET 100. However, as the length of the channel region 121 of the MOSFET 100 is further scaled down, a thin active device area is desired for minimizing the short-channel effects within the MOSFET 100, as known to one of ordinary skill in the art of integrated circuit design.
Thus, a thin active device area is desired for fabricating the drain extension, the source extension, and the channel region of a MOSFET while at the same time the drain silicide and the source silicide of the MOSFET should be fabricated in a thicker semiconductor region for minimizing the series resistance at the drain and source of the MOSFET.
Accordingly, in a general aspect of the present invention, a thin active device area is formed with SOI (semiconductor on insulator) technology such that the drain extension, the source extension, and the channel region of a MOSFET may be fabricated therein while at the same time a thicker semiconductor region is retained such that the drain silicide and the source silicide of the MOSFET may formed therein for fabrication of the MOSFET having scaled down dimensions.
In one embodiment of the present invention, for forming a thin active device area on a SOI (semiconductor on insulator) substrate, an insulating structure is formed on the SOI (semiconductor on insulator) substrate. The insulating structure has an exposed surface. A second semiconductor substrate is pressed down onto the exposed surface of the insulating structure, and a downward force is applied on the second semiconductor substrate against the exposed surface of the insulating structure. The second semiconductor substrate is then removed away from the exposed surface of the insulating structure. The thin active device area is formed of a predetermined thickness of material of the second semiconductor substrate being deposited onto the exposed surface of the insulating structure from the second semiconductor substrate being pressed against the exposed surface of the insulating structure.
The another embodiment of the present invention, the insulating structure is surrounded by a semiconductor material on the SOI substrate, and the predetermined thickness of material of the second semiconductor substrate is deposited onto the semiconductor material surrounding the insulating structure from the second semiconductor substrate being pressed against the exposed surface of the insulating structure.
The present invention may be used to particular advantage when a field effect transistor is formed in the thin active device area with a drain extension, a source extension, and a channel region under a gate of the field effect transistor being formed in the thin active device area. In addition, a drain silicide and a source silicide of the field effect transistor are formed in the thicker semiconductor material surrounding the thin active device area.
In this manner, since the drain extension, the source extension, and the channel region under the gate of the field effect transistor is formed in the thin active device area, short channel effects of the field effect transistor are minimized for the field effect transistor having scaled down dimensions. Furthermore, because a larger volume of the drain silicide and the source silicide may be formed in the thicker semiconductor material surrounding the thin active device area, the parasitic series resistance at the drain and the source of the field effect transistor is minimized such that the speed performance of the field effect transistor is enhanced.
These and other features and advantages of the present invention will be better understood by considering the following detailed description of the invention which is presented with the attached drawings.